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general description the max3822 quad limiting amplifier is ideal for multi- channel systems with data rates up to 2.5gbps. the max3822 operates from a single +3.3v supply, over temperatures ranging from 0c to +85?. a channel- select (cs) pin is provided to program single-, dual-, or quad-channel operation. the disabled channels are shut down to reduce power consumption. the output interface for all four channels is cml. the input can be driven from 20mvp-p to 1000mvp-p differentially. the threshold voltage control is common for all four channels and is programmable by an exter- nal resistor. four separate power detectors are incorpo- rated to monitor the received signal level for each channel. individual ttl-compatible loss-of-power ( lop ) indicators assert low if the channel signal input is below the programmed threshold. typically 4db lop hystere- sis (2db optical) is provided to prevent chattering when the input signal level is close to the threshold. a general lop indicator is also provided which asserts low if one or more of the four inputs is in the lop condition. applications optical system interconnects multichannel receiver modules dense digital cross-connects atm switch networks high-speed parallel links features ? single +3.3v supply ? single-, dual-, or quad-channel operation at 2.5gbps ? 700mw total power dissipation (quad-channel operation) ? 120ps maximum output edge speed ? overall and individual channel loss-of-power ( lop ) indicator ? differential cml outputs with on-chip back termination resistors ? 30ps maximum deterministic jitter ? 2ps random jitter ? power-down feature shuts down unused channels ? operating temperature range: 0c to +85c max3822 +3.3v, 2.5gbps quad limiting amplifier ________________________________________________________________ maxim integrated products 1 out1+ out1- v cc out2+ out2- v cc v cc out3+ out3- v cc out4+ out4- in1+ in1- v cc in2+ in2- v cc v cc in3+ in3- v cc in4+ in4- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 gnd cz4- cz4+ gnd cz3- cz3+ gnd lop lop1 lop2 lop3 lop4 gnd cz1+ cz1- gnd cz2+ cz2- gnd cs gnd gnd vth gnd max3822 top view tqfp-ep pin configuration 19-2144; rev 2; 7/06 ordering information part temp range pin-package max3822ucm 0? to +85? 48 tqfp-ep* max3822ucm+ 0? to +85? 48 tqfp-ep* max3822u/d 0? to +85? dice** * exposed pad. ** contact factory for availability. dice are designed to operate from t a = 0? to t a = +85?, but are tested and guaranteed only at t a = +25?. + denotes lead-free package. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical operating circuit appears at end of data sheet.
max3822 +3.3v, 2.5gbps quad limiting amplifier 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, t a = 0? to +85?, unless otherwise noted. typical values are at v cc = +3.3v and t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage (v cc ) ........................................... -0.5v to +6.0v differential input voltage swing (in1+ - in1-), (in2+ - in2-), (in3+ - in3-), (in4+ - in4-) ..............................................2vp-p voltage at lop1 , lop2 , lop3 , lop4 , lop , cs........................................-0.5v to (v cc + 0.5v) voltage at in1+, in1-, in2+, in2-, in3+, in3-, in4+, in4- .............................(v cc - 1v) to (v cc + 0.5v) voltage at vth .....................................................+0.5v to +2.3v voltage at cz1+, cz1-, cz2+, cz2-, cz3+, cz3-, cz4+, cz4- ........................-0.5v to (v cc + 0.5v) current into out1+, out1-, out2+, out2-, out3+, out3-, out4+, out4-, ..................................?2ma continuous power dissipation (t a = +85?) 48-pin tqfp-ep (derate 29.4mw/? above +85?) ......2.35w operating junction temperature range(die) ...-55? to +150? processing temperature (die) .........................................+400? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units single channel (note 2) 60 72 dual channel (note 2) 110 137 power-supply current i cc quad channel 210 265 ma single-ended data input voltage range v is v cc - 0.5 v c c + 0.25 v single-ended data input resistance 40 50 60 ? r th = 1k ? 14 r th = 649 ? lop assert r th = 400 ? 34 mvp-p r th = 1k ? 4.5 r th = 649 ? 3.0 6.0 lop hysteresis r th = 400 ? 3.4 db cml differential output v od r l = 50 ? to v cc 640 740 1000 mvp-p single-ended data output resistance 40 50 60 ? cml output common-mode voltage v cc - 0.2 v ttl output high v oh sourcing 200? 2.4 v cc v ttl output low v ol sinking 2ma 0.4 v
max3822 +3.3v, 2.5gbps quad limiting amplifier _______________________________________________________________________________________ 3 note 1: characteristics at 0? are guaranteed by design and characterization. dice are tested at t a = +25?. note 2: when power is first applied, all four channels are briefly active. note 3: ac characteristics are guaranteed by design and characterization. note 4: input data edge speed of 150ps (20% to 80%). note 5: data rate = 2.5gbps. measured with 2 13 -1 prbs plus 100 consecutive identical digits. note 6: deterministic jitter (p-p) equals total jitter (p-p) minus random jitter (p-p). note 7: input-referred noise is specified (differential output noise)/(small-signal gain). note 8: measured by applying the same input signal to all channels. skew measurements are made at 50% point of the transition. ac electrical characteristics (v cc = +3.0v to +3.6v, t a = 0? to +85?, unless otherwise noted. typical values are at v cc = +3.3v and t a = +25?.) (notes 1, 3) parameter symbol conditions min typ max units data input voltage range v in 20 1000 mvp-p random jitter (note 4) 2 9.5 ps rms v in = 20mvp-p (notes 5, 6) 8 deterministic jitter v in = 1000mvp-p to 1000mvp-p (notes 5, 6) 430 psp-p data output edge speed (20% to 80%) 90 120 ps lop assert/deassert time 100 ns input-referred noise (note 7) 105 594 ? rm s offset correction low- frequency cutoff cz1 = cz2 = cz3 = cz4 = 0.033? 150 khz channel-to-channel skew (note 8) 20 70 ps
max3822 +3.3v, 2.5gbps quad limiting amplifier 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) 0 2 1 4 3 5 6 8 7 9 0 100 200 300 400 500 600 700 800 900 1000 max3822 toc01 differential input voltage (mv) peak-to-peak deterministic jitter (psp-p) deterministic jitter vs. differential input voltage 0 2 1 4 3 6 5 7 9 8 10 0 200 300 400 100 500 600 700 900 800 1000 random jitter vs. differential input voltage max3822 toc02 differential input voltage (mvp-p) random jitter (ps rms ) electrical eye diagram (v in = 1v differential) max3822 toc03 75ps/div 100mv/div electrical eye diagram (v in = 20mv differential) max3822 toc04 75ps/div 100mv/div electrical eye diagram (v in = 100mv differential) max3822 toc05 75ps/div 100mv/div -90 -70 -60 -50 -40 -30 -20 -10 0 1 10 100 1000 power-supply rejection ratio vs. frequency max3822 toc06 frequency (mhz) power-supply rejection ratio (db) -80 15 -25 110 100 common-mode rejection ratio vs. frequency -15 max3822 toc07 frequency (mhz) common-mode rejection ratio (db) -5 -10 0 5 10 -20 0 20 10 40 30 60 50 70 0 800 400 1200 1600 2000 loss-of-power threshold level vs. threshold resistance max3822 toc08 r th ( ? ) differential input voltage (mvp-p) deassert threshold assert threshold
max3822 +3.3v, 2.5gbps quad limiting amplifier _______________________________________________________________________________________ 5 pin name description 1 in1+ noninverted data input for channel 1 2 in1- inverted data input for channel 1 3, 6, 7, 10, 27, 30, 31, 34 v cc +3.3v supply voltage 4 in2+ noninverted data input for channel 2 5 in2- inverted data input for channel 2 8 in3+ noninverted data input for channel 3 9 in3- inverted data input for channel 3 11 in4+ noninverted data input for channel 4 12 in4- inverted data input for channel 4 13, 16, 19, 37, 39, 40, 42, 45, 48 gnd supply ground 14 cz4- a capacitor connected between this pin and cz4+ extends the time constant for the offset- correction loop associated with channel 4. maxim recommends a capacitor value of 0.033?. 15 cz4+ a capacitor connected between this pin and cz4- extends the time constant for the offset- correction loop associated with channel 4. maxim recommends a capacitor value of 0.033?. 17 cz3- a capacitor connected between this pin and cz3+ extends the time constant for the offset- correction loop associated with channel 3. maxim recommends a capacitor value of 0.033?. 18 cz3+ a capacitor connected between this pin and cz3- extends the time constant for the offset- correction loop associated with channel 3. maxim recommends a capacitor value of 0.033?. 20 lop lop is low when any of the individual power detectors ( lop1 , lop2 , lop3 , lop4 ) are low. 21 lop1 lop1 asserts low when the data input signal level to channel 1 drops below the programmed threshold. 22 lop2 lop2 asserts low when the data input signal level to channel 2 drops below the programmed threshold. 23 lop3 lop3 asserts low when the data input signal level to channel 3 drops below the programmed threshold. 24 lop4 lop4 asserts low when the data input signal level to channel 4 drops below the programmed threshold. 25 out4- inverted data output for channel 4 pin description
max3822 detailed description the max3822 is a 2.5gbps quad limiting amplifier designed for fiber applications with input sensitivities as low as 20mvp-p. this device has internally terminat- ed cml inputs with loss-of-power circuitry for each channel, as well as a general loss-of-power indicator valid for the whole part. offset correction ensures low pulse-width distortion (pwd) and reduced pattern- dependent jitter (pdj). a channel-select (cs) pin is used to control the device? mode of operation as sin- gle, dual, or quad. the inputs of the max3822 are typically connected to a transimpedance amplifier (tia) (max3825) found within a fiber-optic link. the output signal from a tia can con- tain significant amounts of noise, and may vary in amplitude over time. the max3822 limiting amplifier quantizes the input signal, and outputs a voltage-limit- ed waveform over a 40db input dynamic range. signal input to this device passes through a buffer to a linear- gain amplifier. this linear-gain amplifier (figure 1) dri- ves the power-detection circuitry and a chain of limiting amplifiers leading to the cml output buffer. the power-detection circuitry is used to indicate that the data input voltage has fallen below the pro- grammed threshold level. each individual channel has a power detector output ( lop1 , lop2 , lop3 , lop4 ). the lop output is low when any of the individual power- detector outputs are low. a threshold adjustment pin (vth) programs the signal-detect threshold for all four channels with a single external resistor. the offset-cor- rection loop adjusts the input buffer bias until the cml output buffer has a zero offset. this offset-correction loop acts as a high-pass filter where signal components below 150khz are attenuated. input buffer and gain stages the max3822? inputs are terminated with 50 ? to v cc (figure 2). the inputs do not need to be ac-coupled if the upstream tia has cml outputs, but should be ac- coupled if the differential logic levels are in any other format. the differential input signal is passed through a buffer, and then continues through two sets of differen- tial amplifiers, each with an emitter-follower output stage. the first differential amplifier provides approxi- mately 10db gain and a linear output for input signals +3.3v, 2.5gbps quad limiting amplifier 6 _______________________________________________________________________________________ pin name description 26 out4+ noninverted data output for channel 4 28 out3- inverted data output for channel 3 29 out3+ noninverted data output for channel 3 32 out2- inverted data output for channel 2 33 out2+ noninverted data output for channel 2 35 out1- inverted data output for channel 1 36 out1+ noninverted data output for channel 1 38 vth a resistor connected from this pin to ground sets the data input signal level at which the loss-of- power outputs will be asserted. 41 cs channel-select input. to enable channel 1 only, leave cs open. to enable channels 1 and 2, connect cs to v cc . to enable all four channels, connect cs to gnd. 43 cz2- a capacitor connected between this pin and cz2+ extends the time constant for the offset- correction loop associated with channel 2. maxim recommends a capacitor value of 0.033?. 44 cz2+ a capacitor connected between this pin and cz2- extends the time constant for the offset- correction loop associated with channel 2. maxim recommends a capacitor value of 0.033?. 46 cz1- a capacitor connected between this pin and cz1+ extends the time constant for the offset- correction loop associated with channel 1. maxim recommends a capacitor value of 0.033?. 47 cz1+ a capacitor connected between this pin and cz1- extends the time constant for the offset- correction loop associated with channel 1. maxim recommends a capacitor value of 0.033?. ep exposed pad ground. this must be soldered to a circuit board for proper thermal and electrical performance (see exposed pad (ep) package ). pin description (continued)
up to 80mvp-p. this differential amplifier is designed to work with the power-detect circuitry. the next high-gain amplifier provides an additional gain of approximately 22db. this gain stage functions simi- larly to the input-gain stage. the output signal from this gain stage is applied to the cml output buffer shown in figure 3, and is used in the offset-correction loop. the input voltage range is limited to v cc + 0.5v by the esd structure, and to a minimum of v cc - 1v by the internal resistor. figure 2 shows a model of the input stage of the max3822, including the package capaci- tance and the bond wire inductance. the additional 0.4pf capacitance on the inputs represents the esd diode? junction capacitance and a small contribution by the bond pad. for more information about the cml electrical specifications and interfacing to other proto- cols, refer to application note hfan-1.0, introduction to lvds, pecl, and cml . be sure the max3822 is placed as close as possible to the tia when using this device near sensitivity. if you are using a tia with cml outputs, such as the max3825, ac-coupling capacitors are not required. taking these precautions will ensure the best possible sensitivity. output buffer the max3822? cml output buffer is designed to drive 50 ? lines that are used to feed the input of a clock- and data-recovery device (cdr). figure 3 shows a model of the output stage showing some important details. the outputs of the device are terminated internally with 50 ? to v cc . esd diode structures are connected to v cc and gnd. figure 3 also shows the model of the output max3822 +3.3v, 2.5gbps quad limiting amplifier _______________________________________________________________________________________ 7 cz1+ cz1- low pass rectifier and low-pass filter loss-of-power logic r s q out1+ out1- lop1 loss of power lop lop4 lop3 out4- out4+ in4- in4+ out3- out3+ in3- in3+ cz2- cz2+ lop2 out2- out2+ in2- in2+ channel select cs threshold control vth r th in1+ in1- offset correction limiting amplifier #1 limiting amplifier #2 cz3- cz3+ limiting amplifier #3 cz4- cz4+ limiting amplifier #4 buff gain gain cml max3822 figure 1. functional diagram
max3822 stage of the max3822, including package capacitance and bond-wire inductance. the additional 0.4pf capacitance on the output represents the esd diode? junction capacitance and a small contribution by the bond pad. for more information about the cml electri- cal specifications and interfacing to other protocols, refer to application note hfan-1.0, introduction to lvds, pecl, and cml . offset correction each limiting amplifier on the max3822 provides approximately 50db of gain. an input offset as small as 1mv reduces the power-detection circuitry? accuracy and may cause deterministic jitter through an increase of pwd. each of the max3822? integrated limiting amplifiers includes a dc cancellation loop that provides offset correction to the cml output signal in addition to low- frequency power-supply noise rejection. the dc can- cellation loop consists of a low-pass filter and a high-gain amplifier. the input voltage difference of the cml output buffer is amplified, sent through a low-pass filter, inverted, and summed up with the input signal that drives the high-gain input stage. this removes from the output signal all frequency components between the cutoff frequency and dc. the low-frequency cutoff of the dc cancellation loop is set by an external capac- itor connected between cz_+ and cz_-. power detection and threshold control the max3822 incorporates a chatter-free loss-of-power function that is used to determine if the input signal has dropped below the programmed threshold level. the power detector is implemented by comparing the dc- rectified output of the first gain stage to the pro- grammed loss-of-power threshold. the threshold control circuitry enables programming of lop_ assert and deassert reference voltages by using one external resistor, r th (figure 4). an internal amplifi- er guarantees a voltage at v th of approximately 0.5v. the external resistor (r th ) connected to gnd converts this voltage into a current. the current through this resistor sets the power threshold level for the device (see typical operating characteristics , loss-of-power threshold level vs. r th ). +3.3v, 2.5gbps quad limiting amplifier 8 _______________________________________________________________________________________ 50 ? 50 ? esd diodes gnd v cc in+ in- 0.4pf 0.4pf 1.5nh 1.5nh 0.2pf 0.2pf die package figure 2. input structure out- out+ 0.2pf 0.2pf 1.5nh 1.5nh 0.4pf 0.4pf v cc esd diodes 50 ? gnd die package 50 ? figure 3. output structure
loss-of-power logic ( lop ) the loss-of-power logic circuitry is asserted anytime the input power of one of the limiting amplifiers is observed below the threshold set by r th . the logic of this is comprised of two comparators and an s-r flip-flop to compare the outputs of the threshold-control and power-detect circuitry for each of the limiting amplifiers on the max3822. the lop_ output corresponding to a given input is asserted if the input power is too low. a general lop output is also given for the whole part; if any lop_ signal is low, the lop output will also go low. once a lop_ signal has been asserted, the input power must rise above the threshold before resetting. this prevents the lop_ output from turning on and off when the input signal is near the programmed thresh- old level, an effect called chatter. the lop_ indicator will return to its unasserted state when the input power level is increased (4db typ). figure 5 shows the output structure. channel select the channel-select circuitry controls the operating mode of the max3822 by shutting down unused amplifiers. single-, dual-, and quad-mode operation is programmed by the channel-select (cs) pin. when cs is left open, the device is placed into single-mode operation with channel 1 enabled, and channels 2, 3, and 4 disabled. dual- mode operation is programmed by connecting cs directly to v cc . in dual-mode operation, channels 1 and 2 are enabled and channels 3 and 4 are disabled. quad- mode operation is programmed by connecting cs directly to gnd. in quad-mode operation, all four chan- nels are enabled. figure 6 shows the input circuitry of the cs pin. applications information set up the dc cancellation loop the value of the offset-correction capacitor (cz_) affects the maximum speed at which the dc cancella- tion loop can adjust to changes in dc offset at the input. pwd and pattern-dependent jitter (pdj) are both error sources that can be minimized by the proper selection of cz_. therefore, the loop should be as slow as possible to reduce pdj while performing its dc can- cellation function. select the cz_ capacitor to set the bandwidth of the dc cancellation loop. the input impedance between cz+ and cz- is approximately 10k ? . this impedance is in series with cz_. therefore, the low-frequency cutoff (foc) associated with the dc offset-correction loop is computed as follows: max3822 +3.3v, 2.5gbps quad limiting amplifier _______________________________________________________________________________________ 9 vth r th i ctal v ref v cc gnd gnd esd diodes figure 4. threshold set structure esd diodes lop 18k ? 4k ? 2k ? gnd v cc figure 5. ttl output structure
max3822 where 50db is the gain of the offset-correction loop. maxim recommends a value of 0.033? for the filter capacitor. this value will set the lower cutoff frequency of the dc cancellation loop to approximately 150khz. optical hysteresis power and hysteresis are often expressed in decibels. by definition, decibels are always 10log (ratio power). at the inputs to the max3822 limiting amplifier, the power is v in 2 / r. if a receiver? optical input power (x) increases by a factor of two, and the preamplifier is lin- ear, then the voltage input to the max3822 will also increase by a factor of two. the optical power change is: at the max3822, the voltage change is: in an optical receiver, the db change at the max3822 will equal twice the optical db change. the max3822? typical voltage hysteresis is 4db. this provides an opti- cal hysteresis of 2db. exposed-pad (ep) package the exposed-pad, 48-pin tqfp-ep incorporates fea- tures that provide a very low thermal resistance path for heat removal from the ic. the pad is electrical ground on the max3822 and should be soldered to the circuit board for proper thermal and electrical performance. chip information transistor count: 813 substrate connected to gnd process: bipolar die size: 90mil ? 102mil 10 2 10 2 20 2 6 2 2 2 log / / log log vr vr db in in () = () = () =+ 10 2 10 2 3 log log( ) x x db ==+ foc kc db z = 10 210 50 20 ? _ +3.3v, 2.5gbps quad limiting amplifier 10 ______________________________________________________________________________________ 20k ? 40k ? 30k ? cs esd diodes gnd v cc figure 6. channel-select interface max3822 (125.2, 2090.8) (46.9, 1804.6) (1947.6, 1804.6) (1947.6, 46.9) (1985.5, -215) (125.5, -215) (46.9, 46.9) (1804.6, 1966.6) index pad ac d b hf65z y x *orient plot, using hf65z as a key. ? all dimensions are in microns ? gst2 process ? pad dimensions: ? all measurements specify the center of the pad. ? origin is defined as the bottom left corner of the index pad (bonding area) h = 93.8microns w = 93.8microns bond pad information
max3822 +3.3v, 2.5gbps quad limiting amplifier ______________________________________________________________________________________ 11 v cc v cc vth in4- in4+ cs v cc cz4 cz3 cz2 cz1 cz4 cz3 cz2 cz1 out4+ out4- gnd 50 ? in1+ in1- in2+ in2- in3+ in3- in4+ in4- photodiode array lop1 lop2 lop3 lop4 lop r th max3822 50 ? 50 ? 50 ? v cc in3- in3+ out3+ out3- 50 ? 50 ? 50 ? 50 ? v cc in2- in2+ out2+ out2- 50 ? 50 ? 50 ? 50 ? in1- in1+ out1+ out1- 50 ? 50 ? 50 ? 50 ? max3825 typical operating circuit max3822 (hf65z) dimensions side a side b side c side d 46.9 46.9 125.2 2090.8 1947.6 46.9 125.2 -215 46.9 206.2 292.6 2090.8 1947.6 206.2 279.1 -215 46.9 365.5 460.0 2090.8 1947.6 365.5 433.0 -215 46.9 524.8 627.4 2090.8 1947.6 524.8 586.9 -215 46.9 684.1 794.8 2090.8 1947.6 684.1 740.8 -215 46.9 846.1 962.2 2090.8 1947.6 846.1 894.7 -215 46.9 1005.4 1129.6 2090.8 1947.6 1005.4 1048.6 -215 46.9 1167.4 1297.0 2090.8 1947.6 1167.4 1202.5 -215 46.9 1326.7 1464.4 2090.8 1947.6 1326.7 1356.4 -215 46.9 1486.0 1631.8 2090.8 1947.6 1486.0 1510.3 -215 46.9 1645.3 1799.2 2090.8 1947.6 1645.3 1664.2 -215 46.9 1804.6 1966.6 2090.8 1947.6 1804.6 1818.1 -215 1985.5 -215 bond pad information (continued)
max3822 +3.3v, 2.5gbps quad limiting amplifier 12 ______________________________________________________________________________________ out3- v cc out4+ out4- out1+ out1- v cc out2+ out2- v cc v cc out3+ gnd cz1+ cz1- gnd cz2+ cz2- gnd cs gnd gnd vth gnd gnd cz4- cz4+ gnd cz3- cz3+ gnd lop lop1 lop2 lop3 lop4 epgnd in1+ in1- v cc in2+ in2- v cc v cc in3+ in3- v cc in4+ in4- (90mil) ( 102mil) chip topography
max3822 +3.3v, 2.5gbps quad limiting amplifier ______________________________________________________________________________________ 13 48l,tqfp.eps g 1 2 21-0065 package outline, 48l tqfp, 7x7x1.0mm ep option package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3822 +3.3v, 2.5gbps quad limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products. g 2 2 21-0065 package outline, 48l tqfp, 7x7x1.0mm ep option package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) revision history rev 0; 8/01: original data sheet release. rev 1; 7/04: page 1: added lead-free package to ordering information table. rev 2; 7/06: page 11: removed max3827 from typical operating circuit.

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